1. Field of the Invention
The invention relates in general to timing circuits and in particular to an apparatus for generating trigger signal edges in response to selected edges of a repetitive signal pattern.
2. Description of Related Art
Digital integrated circuits (ICs) typically communicate through digital signals having edges synchronized to edges of a periodic clock signal so that state changes in the IC output signals occur at predictable times. However, most such signals exhibit some amount of variation in the timing of their edges (“jitter”) with respect to the clock signal edges. “Random jitter” arises, for example, from random noise in the transmitting IC or in the signal path conveying the signal away from the IC and renders the timing of each data signal edge non-deterministic in that it is not possible for a receiving IC to predict the amount of timing error in any individual signal edge arising from random noise. “Deterministic jitter” arises mainly from frequency response characteristics of the transmitting IC and the signal path conveying the signal from the IC. For example any transmission line will delay signal edges by an amount that is a function of the path's frequency response and the signal's characteristics. When a digital data signal conveys a bit pattern such as {01010101 . . . }, it will act as a relatively higher frequency signal than when it conveys a bit pattern such as {00000111110000011111 . . . }. Thus the amount by which a signal path delays an edge of a digital signal at any given moment depends in part on the particular data pattern the signal currently conveys. This “pattern-dependant” jitter is deterministic in that timing error in each data signal edge due to pattern-dependant jitter for a given pattern is predictable based on the nature of the pattern and on characteristics of the hardware implementing the signal path. Deterministic jitter that is not pattern-dependant can arise, for example, from periodic noise that is coherent with the clock signal the transmitting IC uses to time edges.
Since a signal receiver usually samples a digital signal midway between edges to determine its state, it can tolerate some amount of jitter, but when a signal is too jittery, a signal receiver will not always be able to detect the correct signal state. It is therefore helpful to test ICs to determine whether their output signals exhibit an acceptably small level of jitter.
FIG. 1 illustrates prior art system for measuring the jitter of an integrated circuit device under test (DUT) 10. An IC tester 12 transmits input signals to DUT 10 causing it to produce a periodic output signal OUT. A comparator 14 compares the OUT signal to a reference voltage set to the OUT signal's logic threshold and produces an output signal COMP indicating when the OUT signal crosses the logic threshold. As illustrated in the timing diagram off FIG. 2, a time measurement unit (TMU) 16 measures the period between edges of the COMP signal and edges of a periodic timing reference signal TREF supplied by IC tester 12 and provides data indicating the results of each measurement to a data acquisition system 18. TMU 16 sends a LOAD signal to data acquisition system 18 whenever it has data for the acquisition system to store, and data acquisition system sends a trigger signal TRIG, to TMU 16 whenever it is ready for TMU 16 to make another measurement. TMU 16 responds to the TRIG signal by measuring the interval between the next COMP and TREF signal edges. FIG. 2 shows two such measurements, Tl and T2. The TREF and OUT signals are coherent so if the OUT signal has no jitter, then an edge of the TREF signal will always follow an edge of the COMP signal by a fixed amount and TMU 16 will always measure the same interval between COMP and TREF signal edges. But when the OUT signal is jittery, the period measurements will vary. When TMU 16 makes a large number of such measurements, computer 20 can analyze the resulting data stored in data acquisition system 18 to estimate signal jitter from the variation in the measurement data.
When the OUT signal is periodic and of a single frequency, the test system will be able to detect random jitter, but will not be able to detect any of the deterministic jitter that arises when the OUT signal of a varying frequency. Suppose, however, the OUT signal were periodic, but had a progressively decreasing frequency during each cycle so that signal frequency during each cycle ranges from the highest possible frequency down to DC. FIG. 3 illustrates the COMP signal output that might result from such an OUT signal. In order to properly measure the jitter of this signal, TMU 16 would have to make several period measurements of representative edges of the COMP signal at each of several frequency ranges of interest. The problem with the test system of FIG. 1 is that data acquisition system 18 asserts the TRIG signal that initiates period measurement whenever it is ready to acquire more data. Since the TRIG signal is asserted at the rate TMU 16 and data acquisition circuit 18 can acquire and store data, there is no assurance that the appropriative number of period measurements will be made at each OUT signal frequency range of interest.
What is needed is a triggering circuit for controlling the TRIG signal so that TMU 16 samples selected corresponding edges within each cycle of the COMP signal a predetermined number of times in a predetermined order. In such case, the data sequence produced by THU 16 would be ordered so that computer 20 would he able to determine the range of edge timing variation at each frequency range of interest, thereby enabling it to quantify both deterministic and nondeterministic jitter.